Sr.No
1
|
CISC
Founded in 1970’s
|
RISC
Founded in late 1980’s
|
2
|
Needed more number of clock cycles
|
Designed to work with less or limited number of clock cycles. Usually 1 clock.
|
3
|
These had slow memories coupled to processor built using many simple IC’s.
|
Could be coupled with faster memories
|
4
|
The processor was controlled by microcode ROM’s, which were faster than processor.
|
The processor itself was faster and interfacing other interface did not much affect the overall speed.
|
5
|
Code can execute X86 machines code
|
Code cannot execute code for X86
|
6
|
Older CISC did not support pipeline
|
Supports pipelining
|
7
|
Variable Instruction length
|
Fixed instruction length.
|
8
|
Allows value in memory to be used as operands for data processing
|
Can work only if data is in registers and not in memory directly.(LOAD & STORE )
|
9
|
Have very good code density
|
Have very poor code density.
|
10
|
Hardware complexity is less
|
Hardware complexity is more.
|
Showing posts with label Controlled. Show all posts
Showing posts with label Controlled. Show all posts
Wednesday, 11 December 2013
Basic Introduction of CISC & RISC for Embedded Engineers
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