INTRODUCTION TO CPU REGISTER

CPU Registers

The ARM CPU provides in user mode 16 general purpose registers (R0 - R15) and a Program Status Register (PSR). By software and hardware conventions, the following register have a special meaning:

• R13 is used as stack pointer (SP) that holds the current stack address
• R14 is used as link register (LR) that saves return address for the BL and BLX instruction,
• R15 is used as program counter (PC) that points to the executed instruction.

The ARM CPU provides shadow registers which are selected on a Operation Mode switch. These shadow registers reduce interrupt latency. All CPU Register are shown in the following picture. 

SP: Stack pointer

LR: Link register

PC: Program counter

CPSR: Current Program Status Register.

SPSR: Saved Program Status Register.

LR (Link register): is used by the processor when there is a branch operation which occurs due to function call or due to some condition checking.

When the processor is executing and there is a need to branch to other location the return address (the address from where the execution is to be started, returning after completing the function execution). If there are multiple function calls then LR will store only the last address before jumping.

CPSR: Used to store the important back-up data whenever there is change of any mode.

E.g if the processor is executing user mode and there is a interrupt, before going to service the interrupt the all the data and the status registers and the current mode of operation information is stored in CPSR.

CPSR registers are present in all the 7 modes but are not usually shown.

SPSR: .Stores the copy of CPSR register in which ever mode the processor enters. All the 7 modes have SPSR registers and are shown in the mode registers

If the processor switches from USER mode to IRQ mode because of an IRQ, the CPSR value is updated in the user mode and the processor switches to IRQ mode. Before starting the IRQ code execution the value of CPSR is copied to SPSR of IRQ mode.

While executing IRQ mode and high priority interrupt occurs (FIQ) then the status of the IRQ mode is updated in its CPSR register and when the processor switches to FIQ mode the contents of CPSR in IRQ mode is copied to SPSR register in FIQ mode.